Low Power Analog CMOS for Cardiac Pacemakers e-bog

Power reduction is a central priority in battery-powered medical implantable devices, particularly pacemakers, to either increase battery lifetime or decrease size using a smaller battery. Low Power Analog CMOS for Cardiac Pacemakers proposes new techniques for the reduction of power consumption in analog integrated circuits. Our main example is the pacemaker sense channel, which is representative of a broader class of biomedical circuits aimed at qualitatively detecting biological signals. The first and second chapters are a tutorial presentation on implantable medical devices and pacemakers from the circuit designer point of view. This is illustrated by the requirements and solutions applied in our implementation of an industrial IC for pacemakers. There from, the book discusses the means for reduction of power consumption at three levels: base technology, power-oriented analytical synthesis procedures and circuit architecture. At the technology level, we analyze the impact that the application of the fully depleted silicon-on-insulator (FD SOI) technology has on this kind of analog circuits. The basic building block levels as well as the system level (pacemaker sense channel) are considered. Concerning the design technique, we apply a methodology, based on the transconductance to current ratio that exploits all regions of inversion of the MOS transistor. Various performance aspects of analog building blocks are modeled and a power optimization synthesis of OTAs for a given total settling time (including the slewing and linear regions) is proposed. At the circuit level, we present a new design approach of a class AB output stage suitable for micropower application. In our design approach, the usual advantages of the application of a class AB output stage are enhanced by the application of a transconductance multiplication effect. These techniques are tested in experimental prototypes of amplifiers and complete pacemaker sense channel implementations in SOI and standard bulk CMOS technologies. An ultra low consumption of 110 nA (0.3u W) is achieved in a FD SOI sense channel implementation. Though primarily addressed to the pacemaker system, the techniques proposed are shown to have application in other contexts where power reduction is a main concern.